News Release from: 1st Silicon (Malaysia)
Edited by the Electronicstalk Editorial Team on 17 September 2002

Phase-lock loop IP joins foundry portfolio

SoC designers can now access essential Parthus phase lock loop intellectual property from 1st Silicon as part of the 1st Silicon (Malaysia) foundry service.

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1st Silicon (Malaysia) SoC designers can now access essential Parthus phase lock loop (PLL) intellectual property (IP) from 1st Silicon as part of the company's foundry service. "Foundries play a key role in delivering silicon-proven IP cores that form the central building blocks essential to system-on-chip designs", said Dr W John Nelson, Chief Operating Officer of 1st Silicon. "We've chosen Parthus for their flexibility and timely creation of PLLs on demand, and because they offer industry-leading jitter performance that is well recognised among the design community".

"We are delighted to have 1st Silicon as a licensee for our innovative PLLXpert technology", said John Ryan, VP and General Manager of Wireline and Mixed-Signal at Parthus Technologies.

"By choosing PLLXpert Online, 1st Silicon are providing their customers with a technology design platform that reduces the cost and speeds the time-to-market for their silicon products".

As the first phase of the agreement, 1st Silicon will verify the Parthus PLL IP in silicon using a test chip containing multiple PLL instantiations designed to exercise the extremes of the design range.

Further verification will be completed through simulations using an automated test bench designed to test all valid PLL configurations in 1st Silicon's 0.25- and 0.18-micron CMOS process technologies.

Clock synthesis cores (PLLs) remain one of the most challenging technology blocks to develop, and they continue to impose considerable risk on the successful deployment of IC products.

Parthus' PLLXpert, an online PLL generation engine, enables the design of risk-free, silicon-proven PLLs in minutes - shortening the typical development time by months.

Through PLLXpert's user interface, 1st Silicon customers can design and deploy silicon proven, high-performance PLL cores in minutes online through www.PLLXpert.com.

No prior training, in-depth PLL design knowledge or additional EDA tools are required.

A 1st Silicon customer receives personalised datasheets, Verilog models, and other front-end deliverables at no charge.

IP cores in GDSII format can be delivered in minutes DRC and LVS to 1st Silicon registered users.

The software can be accessed through the Parthus website in October of this year.

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