Memory compilers streamline SoC design
The SiWare Memory compilers and SiWare Logic libraries provide designers with options for maximum flexibility in effectively managing design tradeoffs to meet their specific requirements.
Virage Logic has released the memory compilers and logic libraries for TSMC's 40nm process The new SiWare product portfolio provides semiconductor companies with 40nm physical IP that is designed to enable System-on-Chips (SoCs) to run faster, manage power more efficiently, use less area and achieve higher manufacturing yields
The SiWare product line, first introduced in October 2007 for the 65nm process, addresses the increasingly complex design requirements placed on physical IP at advanced process nodes.
The SiWare Memory compilers and S