Line of 65nm timing IP planned for 2007
True Circuits has announced a new line of silicon-proven TSMC 65nm phase-locked loop (PLL) and delay-locked loop (DLL) hard macros targeting high-speed timing applications
True Circuits (TCI), a provider of analogue and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries has announced a new line of silicon-proven TSMC 65nm phase-locked loop (PLL) and delay-locked loop (DLL) hard macros targeting high-speed timing applications.
True Circuits has already licensed this IP to customers who have incorporated it into products that will begin shipping in 2007.
True Circuits has also been working closely with other leading silicon foundries and IDMs on the porting and silicon testing of its PLLs and DLLs in their 65nm processes.
'Our continued focus on RandD and our proven design methodology allow us to quickly and reliably port our designs to advanced processes so our customers have the high-performance timing IP they will need to accelerate their 65nm product development,' remarked Stephen Maneatis, True Circuits, CEO.
'We have licensed 65nm PLLs and DLLs to a number of key TSMC customers during the last year and are seeing strong demand for our industry-leading timing technologies across a number of industry segments'.
True Circuits' 65nm PLL and DLL designs are based on TCI's industry-leading analog timing circuits that have been used in hundreds of customer products in 0.25um to 90nm processes with many different foundries and IDMs.
TCI has extensively characterized this new line of PLL and DLL hard macros for optimal 65nm performance and continues to engage with key partners and customers in the development and silicon testing of test chips and pre-production products.
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