Tensilica announces customisable processor
Tensilica has introduced the Xtensa 8 customisable processor, the eighth generation of its low-power dataplane processor cores (DPUs).
With power dissipation starting at just 12uW/MHz, the Xtensa 8 processor core starts at a size of just 15,000 gates and consumes less than 0.05mm2 in 40nm process technology.
Designers using an Xtensa 8 DPU can select from an expanded library of pre-verified configuration options to get the exact functionality they need.
Enhancements in this new generation processor include pairs of 32-bit GPIO (general purpose input/outputs) and 32-bit Queue interfaces for direct connection to RTL (register transfer level) blocks, and a low-area, double-precision floating-point accelerator.
As the Xtensa 8 processor core can be customised, designers have a wide range of choices available to meet area, power and performance requirements.
Full synthesis scripts are provided for all major EDA vendors allowing designers to target their favourite libraries and processes.
A typical small configuration consumes 17uW/MHz of power while occupying 0.046mm2 in TSMC 40LP process technology.
That same configuration, synthesised for maximum performance in the same process technology, can run up to 540MHz and still only consumes 25uW/MHz of power with an area of 0.074mm2.
The Xtensa 8 processor core can be customised with configuration check-box options that provide control and data input/output capabilities that entirely bypass the main system bus.
This allows direct connectivity to blocks of RTL in the SOC, providing fine-grained, low-latency control of those hardware blocks.
These connections also allow Xtensa 8 DPUs to stream data to RTL blocks at much higher speeds to improve system performance.
The 32-bit GPIO (general-purpose input output) interface provides 32-bit input and 32-bit output control and status information exchange, which is naturally accessed directly as registers from the processor's regular instruction set.
This interface is suitable for peripheral control and monitoring.
The 32-bit input and 32-bit output Queue interfaces operate like FIFO (first in, first out) interfaces, providing a high-bandwidth and low latency mechanism for streaming data to and from other blocks in the system or other Xtensa processors.
To the programmer's viewpoint, input and output queue data is register based for simple and quick access - there is no need to load or store the data before and after any computation.
Tensilica added a lightweight, double-precision floating-point acceleration (FPA) option.
It is small in area, consumes less than 7K gates and helps speed up applications that require high-precision, low-bandwidth data operations, such as in motor control or GPS software stacks.
This acceleration option is provided in addition to the existing single precision FPU (floating point unit) option.
Tensilica also added enhanced SOC infrastructure choices, including AMBA AHB-Lite and AXI bridges with asynchronous or synchronous clocks and synchronous/asynchronous reset capabilities.
Tensilica's Xtensa processor cores are completely backwards compatible, meaning that code written for the first-generation Xtensa processors will still run on the Xtensa 8 processor.
This allows designers to quickly migrate to new versions in order to take advantage of the power savings, performance improvements and additional functionality.
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