On-the-fly error correcting code
Tensilica has introduced its seventh-generation of Xtensa configurable processors, the Xtensa LX2 and Xtensa 7 cores.
Tensilica has introduced its seventh-generation of Xtensa configurable processors, the Xtensa LX2 and Xtensa 7 cores Both processors feature several architectural enhancements, and are the first configurable licensable core families available with built-in, on-the-fly Error Correcting Code (ECC), which is extremely important in storage, networking, automotive and transaction processing applications where data integrity and error resiliency are of paramount concern
Tensilica's new generation of processors reinforce Tensilica's processor technology leadership by remaining the lowest power, highest performance licensable cores on the market.
Both processors are available and shipping now.
"We've made several architectural enhancements that enhance our leadership both with our Xtensa 7 our Xtensa LX2 configurable, extensible processors," stated Chris Rowen, Tensilica's president and CEO.
"Tensilica offers more configuration options and a much more automated process of generating both the hardware RTL and the matching software tool chain than anyone in the industry".
The base Xtensa instruction set architecture, common to both the Xtensa 7 and Xtensa LX processor cores, provides the industry's lowest power and highest performance when compared to legacy fixed architecture cores.
Because both cores are fully configurable and designers can add application-specific instructions to the base processor using Tensilica's patented, automated processor generator, it's important to compare equivalent processor configurations when comparing to competing processor core offerings.
For example, a small configuration of an Xtensa 7 core without cache memories and without designer-defined instruction extensions is roughly equivalent to an ARM 7TDMI-s core, yet it has much better performance and lower power: A high-performance version of the Xtensa LX2 processor uses less than half the die area and power of the equivalent ARM 1136J-S: NOTE: This is not the base Xtensa LX processor.
Rather, this version of Xtensa LX2 has been configured to be a high performance, general-purpose CPU.
Several enhancements were made to both the Xtensa 7 and Xtensa LX2 processors to reduce power up to 30 percent in total core plus memory power, including: Enhanced configuration choices that allow independent width selection of main system memory interface, local data memory interface, and instruction memory interface; Reduced execution speculation for data memory enables and accesses, leaving data cache and tightly coupled local data memories turned off for longer periods of time; An optional wider instruction fe