IP agreement provides
memory density boost
High-density SRAM-1T memory IP enables integration of up to three times more memory than a standard 6T-SRAM, enabling chips to incorporate more system memory on-chip
Synopsys and Novelics have added an SRAM-1T embedded memory IP to Synopsys' DesignWare IP portfolio. It is implemented in bulk logic CMOS technology, requiring no additional manufacturing costs. As part of a co-operative technology licensing and development relationship with Novelics, Synopsys will also offer a family of standard SRAM IP.
The new silicon-proven DesignWare embedded memory IP will enable the design and manufacturing of higher performance and more power efficient system-on-chips (SoCs).
Content and feature-rich products require faster, more power efficient SoCs with increasingly large amounts of on-chip memory.
High density SRAM-1T memory IP enables integration of up to three times more memory than a standard 6T-SRAM, enabling chips to incorporate more system memory on-chip, thus lowering power and overall system cost.
The DesignWare coolSRAM-1T is implemented on a bulk logic CMOS process and does not require additional masks or manufacturing steps.
This implementation provides designers with a true zero added cost solution, offering up to 15% reduction in manufacturing costs compared to existing SRAM-1T products.
The DesignWare coolSRAM-1T memory IP is a compiler-based solution providing designers with immediate access to the specific memory IP instance they need without any compromise on instance storage capacity or topology.
The combination of not having to pay a premium on wafer price coupled with the flexibility of the compiler-based technology enables designers to reduce system level power and cost, even for designs with small amounts of memory.
In addition to the SRAM-1T offering, Synopsys will provide a family of high-performance and low power standard SRAMs that include single port 6T, dual port 8T, register file and ultra high density ROM.
The new DesignWare coolSRAM memory IP enables the implementation of a 32Kbyte cache memory, operating well over 1GHz while drawing less than 6uW/MHz as measured on a 65nm low power process.
The compilers also include advanced power control features such as leakage control and block level sleep mode to implement system level power management, enabling increased battery life for portable devices.
'Embedded memory often represents well over 50% of the transistors on a chip and therefore plays a crucial role in a designer's ability to differentiate their designs', said Joachim Kunkel, Vice President and General Manager of the Solutions Group at Synopsys.
'Synopsys is expanding into this high-growth IP market with a SRAM-1T embedded memory IP solution that allows designers to lower system cost and integration risk, while also offering a set of standard SRAMs that provides low-power and high-performance characteristics'.
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