65nm process PHY meets USB specs
USB 2.0 PHY is first IP for TSMC's 65nm process to successfully pass the USB Implementers Forum High-Speed On The Go PHY certification.
The Synopsys DesignWare USB 2.0 nanoPHY has become the first USB 2.0 PHY intellectual property (IP) for TSMC's 65nm process to successfully pass the USB Implementers Forum High-Speed On The Go (OTG) PHY certification Synopsys' industry leading USB 2.0 nanoPHY mixed signal IP, now available in the TSMC 65nm process nodes, uses half the power and die area compared with previous USB solutions and enables faster time to market and reduced risk
In addition to optimising for low power and area, Synopsys IP architects designed the DesignWare USB 2.0 nanoPHY for long term electrical performance of the USB 2.0 nanoPHY when implemented in the 2.5V transistor process option.
As the nanoPHY must maintain USB compliance and thereby support 3.3 and 5V signalling levels, careful attention was required to ensure that the 2.5V structures would not be overstressed.
Extensive simulations were specifically developed across worst case conditions to ensure consistent, long term nanoPHY operation.
The DesignWare USB 2.0 nanoPHY is part of the complete USB OTG solution from Synopsys.
Combined with Synopsys' USB 2.0 high speed OTG controller and USB Verification IP, Synopsys offers a proven 65nm solution for high speed OTG applications.
The DesignWare USB IP products, including the PHYs have been certified in hundreds of applications.
"Designers require that we provide them access to reliable, low risk and proven mixed signal connectivity IP such as USB 2.0", said Kuo Wu, Deputy Director of Design Service Marketing at TSMC.
"This latest generation of USB 2.0 nanoPHYs from Synopsys allows designers to quickly integrate USB 2.0 connectivity into their system on chip designs and ramp into high volume production".
Synopsys' USB 2.0 nanoPHYs are available for TSMC's 65nm, 90nm, and 130nm processes.
"The availability of proven mixed signal IP continues to be a key factor in enabling migration of SoC designs to advanced small geometry processes", said John Koeter, senior director of IP Marketing at Synopsys.
"We've worked closely with TSMC in creating this 65nm USB 2.0 nanoPHY IP to help designers achieve power and area savings while meeting TSMC's rigorous design for manufacturing standards".
"Our attention to these details provides designers the confidence that the nanoPHY will deliver low power, small area, maximum yield and long term reliability".
Synopsys' DesignWare USB 2.0 nanoPHY IP is available now from Synopsys for TSMC's 65, 90 and 130nm processes.
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