News Release from: Synopsys
Edited by the Electronicstalk Editorial Team on 3 July 2006
USB 2.0 IP runs on TSMC's 90nm LP process
The DesignWare USB 2.0 nanoPHY IP is Synopsys' next-generation USB 2.0 mixed-signal PHY targeting low-power and consumer applications.
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Synopsys has announced the immediate availability of the DesignWare USB 2.0 nanoPHY intellectual property (IP) for Taiwan semiconductor manufacturing Company's (TSMC's) Nexsys 90nm low-power process. The DesignWare USB 2.0 nanoPHY IP is Synopsys' next-generation USB 2.0 mixed-signal PHY targeting low-power and consumer applications. The DesignWare nanoPHY IP for TSMC's 90nm process was developed with TSMC's proven Nexsys standard cell libraries, which TSMC designed according to their 90nm design-for-manufacturing rules.
This gives system-on-chip (SoC) designers a proven PHY, which lowers risk and enables predictable results.
The DesignWare USB 2.0 nanoPHY IP is Hi-Speed USB logo-certified and requires half the power and die area compared with previous-generation solutions.
Ideal for applications requiring longer battery life and lower silicon cost, the DesignWare nanoPHY IP will benefit next-generation handheld game machines, feature-rich smart phones, digital cameras and portable audio/video players.
A single-port, on-the-go (OTG) configuration takes up only 0.6mm2 of area and consumes less than 30mA of current during high-speed data transmission.
The DesignWare nanoPHY IP is also tunable for optimal yield by enabling adjustments in key PHY performance parameters to address effects related to process variation as well as package- or board-level issues.
'TSMC and Synopsys have worked together to ensure that designers have access to quality USB PHYs for our leading 90nm processes', said Ed Wan, Senior Director of Design Service Marketing at TSMC.
'The combination of DesignWare USB 2.0 nanoPHY IP and TSMC's Nexsys standard cell libraries provide the industry with low-power, cost-effective USB IP'.
'As the leader in USB IP, we collaborate with TSMC to deliver IP solutions that enable our customers to meet critical market windows', said Guri Stark, Vice President of Marketing for the Solutions Group at Synopsys.
'Our complete and silicon-proven USB IP product line, including PHYs, digital controller cores and verification IP, enables designers to integrate high-quality USB IP into their next-generation portable and consumer electronic applications'.
The DesignWare USB 2.0 nanoPHY IP is available today in TSMC's 90-LP process.
The complete set of TSMC Nexsys standard cell libraries is available today at no additional cost to DesignWare Library licensees.
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