Interface IP eases USB 2.0 integration
New USB 2.0 PHY IP is tailored specifically for low power consumption, small area and high yield
Synopsys has added the new DesignWare USB 2.0 nanoPHY IP to its existing DesignWare USB 2.0 physical layer (PHY) product line. The new mixed-signal PHY IP builds on Synopsys' three years of leadership in successfully providing USB 2.0 PHY intellectual property (IP) in more than two dozen process node and configuration combinations.
The new DesignWare USB 2.0 nanoPHY IP is tailored specifically for low power consumption, small area and high yield.
It targets designers of mobile, high-volume consumer applications such as next generation handheld game machines, feature-rich smart phones, digital cameras, and portable audio and video players.
Over the last three to four years, designers have successfully integrated the USB 2.0 bus interface into many systems-on-chip (SoC) designs.
The initial applications started with PCs and then moved into peripherals such as printers, scanners, and external hard drives that were typically plugged into a power source.
However, as the bus standard has become more pervasive, it has been quickly adopted into a wide range of battery powered consumer applications that are more cost sensitive and require very low power.
'This new DesignWare USB 2.0 nanoPHY IP follows many years of success with our volume-proven USB PHY IP solution', said Guri Stark, Vice President of Marketing, Solutions Group at Synopsys.
'Our experience with leading semiconductor companies has enabled us to continuously innovate and address our customers' needs for low-power cost-competitive IP that helps deliver high yield, reduced area and increased interoperability'.
'As part of our complete USB IP solution, we expect the new PHY IP to be adopted in many cost- and power-sensitive designs for the competitive mobile and consumer market'.
The new DesignWare USB 2.0 USB nanoPHY IP is expected to be available in Q1 of calendar 2006.
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