Verification platform proves complex switch chips
StarGen has successfully verified two large, complex switching chips using VCS comprehensive RTL verification, Vera testbench automation and VCS Verification Library solutions.
StarGen, the innovation leader in advanced interconnect semiconductors, has successfully verified two large, complex switching chips using Synopsys' VCS comprehensive RTL verification, Vera testbench automation and VCS Verification Library solutions from the Discovery Verification Platform.
These chips use the StarGen AXSys architecture for performance, flexibility, reliability and scalability, leveraging both the Advanced Switching Interconnect (ASI) and PCI Express standards for connectivity.
AXSys is an ideal board and system level interconnect solution for system OEMs in the computing, storage and communications sectors.
"We found the combination of the VCS and Vera solutions to be extremely powerful in verifying our Merlin Switch and Kestrel PCI Express-ASI bridge chips", said Ernie Grella, Director of Chip Development at StarGen.
"Vera's parallel constraint solver, with its high performance and ability to solve constraints over arrays, was essential for setting up efficient and effective chip level testbenches".
"We used both assertions and functional coverage within the Vera tool to enhance our verification environment".
"We are currently migrating our environment to the VCS Native Testbench (NTB) technology to achieve even greater performance".
The StarGen engineering team used Vera-based testbenches for stand-alone verification of major blocks as well as for full-chip verification.
StarGen's methodology took advantage of DesignWare PCI Expres verification IP (VIP) from the Synopsys VCS Verification Library to validate conformance to the industry standard interface protocol.
The VIP in the VCS Verification Library tightly integrates with the Synopsys Reference Verification Methodology and supports native compilation by VCS NTB for higher performance.
"Verification success requires a combination of technologies, linked by a comprehensive methodology", said Farhad Hayat, Vice President of Marketing, Verification Group, Synopsys.
"Constrained-random stimulus generation, coverage-driven verification, assertions and verification IP each play a part in ensuring that chips can be taped out on time with first-silicon success".
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