ASIC designer accelerates chip development
Silicon Logic Engineering is using the VCS comprehensive RTL verification solution and Vera testbench automation tool to accelerate its chip development process.
Silicon Logic Engineering (SLE), a provider of high-end ASIC and system design services, has adopted Synopsys' VCS comprehensive RTL verification solution and Vera testbench automation tool to accelerate its chip development process.
SLE is taking advantage of the Synopsys Reference Verification Methodology (RVM) to reduce the development time for its verification environment and to ensure the highest-quality verification results.
In addition to the VCS solution and Vera tool, SLE has adopted Synopsys' Magellan hybrid formal analysis, Leda RTL checking and Formality formal equivalency checking solutions from the Discovery Verification Platform.
"We chose Synopsys as our verification partner on our latest 90-nanometre, 40-million-gate chip development project after evaluating several providers", said Bob Solberg, Vice President of Operations and cofounder at SLE.
"Synopsys was able to deliver the breadth of tools, proven methodology and responsive support we needed to be confident in our aggressive schedule and quality targets".
"In particular, Synopsys' RVM enables us to cut our verification development time, while promoting industry best practices within our verification team".
"The collaborative relationship we have with the Synopsys teams was also a significant factor in our decision making process".
The Synopsys Reference Verification Methodology, delivered with VCS Native Testbench technology and the Vera tool, helps engineers to quickly implement and deploy advanced verification environments using modern constrained-random, coverage-driven and assertion-based verification techniques.
The RVM speeds verification development by providing predefined base-class libraries with advanced features for transaction modelling, transactor construction, messaging services, verification flow, assertion checkers, and more.
In addition, Synopsys provides extensive RVM documentation and offers training to enable both small and large chip development teams to quickly implement industry best practices for verification.
"Synopsys' RVM enables chip developers to rapidly adopt the proven verification techniques used by the experts", said Farhad Hayat, Vice President of Marketing, Verification Group, Synopsys "With support in the Vera tool and in VCS Native Testbench technology for even higher performance, the RVM enables ASIC and system developers such as SLE to complete their projects with a higher level of verification confidence in less time".
SLE specialises in right-first-time, leading edge, digital application specific integrated circuits (ASIC) and system design services.
SLE's proven and repeatable Think Physical design process, tools, and semiconductor intellectual property reduce time to market and are provided by one of the most experienced VLSI design teams in the industry.
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