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Testbench technology aids RTL verification

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Edited by the Electronicstalk editorial team May 27, 2004

The latest release of the VCS RTL verification solution extends its built-in testbench capabilities to include a rich set of advanced technologies.

The latest release of the VCS RTL verification solution extends its built-in testbench capabilities to include a rich set of advanced technologies for RTL verification.

These advancements include support for the same next-generation constraint-solver engines used in the Vera testbench automation tool, support for object-oriented testbench architecture, and advanced data types.

With the addition of these new capabilities, engineers can use VCS to create and run powerful constrained-random testbenches using a single unified tool for maximum productivity and improved overall verification run time by up to five times, including simulation of design, testbenches and assertions, compared with standalone testbench tools working with VCS.

"We are continuously improving our verification methodologies", said Shrenik Mehta, Director of Frontend Technologies, Scalable Systems Group at Sun Microsystems.

"By using the testbench and assertion capabilities built into VCS, our engineers are able to write powerful testbenches that run faster compared to other standalone solutions from Synopsys, allowing us to run more verification cycles in the given time".

"This is extremely useful in reducing the development cycle as we design our next-generation chip multithreaded (CMT) processors for throughput computing".

VCS now has built-in support for the same proven, next-generation constraint-solver engines used in the Vera testbench automation product.

The multiple solver engines simultaneously analyse all user-specified constraints to rapidly generate high-quality random stimulus to simulate the design for corner-case behaviour.

These engines will find a solution to user constraints, if one exists, minimising constraint conflicts and maximising verification productivity.

In addition to many testbench constructs already supported, other new built-in testbench technologies, natively supported in VCS, include: support for object-oriented programming; advanced data types, such as dynamic arrays and associative arrays; random stream generation capability; virtual ports; and a DirectC interface.

With the addition of object-oriented programming support in VCS engineers can create reusable and easily extendable testbench infrastructure.

The addition of advanced data types improves verification productivity by allowing engineers to write compact yet powerful testbenches.

The built-in stream generator in VCS can now be used to create random combinations of transactions or microprocessor instructions.

This capability allows engineers to verify the design under numerous operating scenarios that are difficult to create manually, thus increasing the quality of the design.

"To deliver our highly integrated VLSI solutions used in global communications equipment, we verify our designs in many different configurations using constrained random testbench techniques", said Chris Kniker, Principal Member of Technical Staff at TranSwitch, a provider of high-speed VLSI semiconductor solutions.

"By using the full-featured testbench capabilities in VCS, such as object-oriented programming and constraint-solver engines, we are able to deploy a comprehensive testbench environment to thoroughly verify our designs".

"Additionally, the built-in technologies in VCS have allowed us to run our regressions in half the time as compared to previous standalone approaches".

VCS natively compiles OpenVera testbench code into the simulation engine delivering up to five times speed up of the overall verification environment.

The performance improvements are realised by applying VCS' advanced optimisation algorithms to the combination of testbench and RTL code, as well as eliminating the communication overhead of separate testbench and HDL simulation tools.

"Our customers continue to require additional performance and capacity to meet the verification demands of their complex SoC designs", said Farhad Hayat, Vice President of Marketing at Synopsys.

"By natively compiling the advanced Vera testbench technology into VCS, we continue to deliver higher performance and simulation capacity to enable our customers to meet their aggressive verification goals while finding more complex bugs in their designs".

All the enhancements are available immediately with the 7.1 release of VCS.

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