News Release from: MIPS Technologies
Edited by the Electronicstalk Editorial Team on 14 May 2002
CoWare helps MIPS with design environment
MIPS Technologies and CoWare are aiming get new MIPS-based SoC designs to market faster by cutting design time and streamlining hardware and software development.
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MIPS Technologies and CoWare are aiming get new MIPS-based SoC designs to market faster by cutting design time and streamlining hardware and software development. Under a new agreement, the two companies will create a powerful new SoC design environment that integrates MIPS Technologies' higher level simulation models of the MIPS32 4KEc, MIPS64 5Kc, MIPS64 5Kf and MIPS64 20Kc high-performance processor cores and key peripherals into the CoWare N2C design system. Designers will be able to take advantage of CoWare's extensive system-level simulation and analysis tools to help determine the best bus architecture and hardware/software partitioning in order to strike the right balance between processor performance and overall system cost in terms of area or power.
Designers also will be able to use CoWare's patented interface synthesis technology to automate the creation of hardware and bus interfaces as well as the software drivers, significantly speeding new designs to market and making trade-off analysis much easier.
"By teaming with CoWare, we can provide an environment that will help our customers determine how the MIPS32 or MIPS64 architectures can best meet their performance goals", said Brad Holtzinger, director of system solutions at MIPS Technologies.
"With CoWare N2C, our customers are able to start at a high level of abstraction for HDL-based approaches.
CoWare has demonstrated that its design environment can significantly reduce SoC design time.
We're delighted to be working with CoWare to help bring this productivity improvement to our customers".
Alan Naumann, CoWare's president and CEO, added, "The MIPS architecture is used extensively in demanding, high-performance applications.
By teaming with MIPS Technologies, we're broadening our solution scope to include the large base of MIPS developers.
We're proud that our system-level design environment can meet the needs of MIPS Technologies' most advanced customers".
Different architectures can make a tremendous difference in power and performance.
In several cases, up to a 50% difference in performance has been noted between different hardware/software partitionings and architectures.
The new CoWare design environment will allow designers to efficiently evaluate the industry-standard 32- and 64bit MIPS architectures to find the optimal trade-offs for the newest products in the networking and consumer device markets, such as set-top boxes, in-car entertainment, digital televisions and cameras, video game controllers, switches and routers, and office automation equipment.
This new integrated SoC design environment also will allow designers to more fully evaluate the effects of different hardware/software design tradeoffs, analyse CPU loading, determine the optimum memory configuration, and make sure that the hardware and software continue to work together as the design is finalised.
Designers will be able to use the design environment to develop a virtual platform so that software development can start earlier and concurrently with hardware design.
As low-level drivers, middleware, operating systems and embedded applications are developed, this software can be verified with the hardware model.
The virtual platform also can be used to dramatically reduce the time needed to create derivative designs.
By creating one "core" platform that can be extended in a variety of ways for different designs, companies can leverage their design investments several times over.
The design environment integrates with most popular design and development tools.
Any algorithm-design tool that outputs SystemC code, the de facto standard design language for system design, or ANSI C code can provide input to the design environment.
For hardware designers, the design environment supports all of the popular register-transfer-level (RTL) simulators, both Verilog and VHDL, as well as leading RTL and behaviour synthesis tools.
For software developers, the design environment supports existing C/C++ design flows, including the import of existing libraries, and is compatible with the leading MIPS-based compilers, debuggers and RTOS tools.
CoWare and MIPS Technologies expect to complete the IP integration process necessary to make the new design environment available to customers starting in Q3 2002.
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