MIPS cores join Synopsis IP library
More than 25,000 design engineers who use the Synopsys DesignWare IP library to jump-start their designs will soon have access to the MIPS Technologies highly configurable MIPS32 4KE family of synthes
More than 25,000 design engineers who use the Synopsys DesignWare IP library to jump-start their designs will soon have access to the MIPS Technologies highly configurable MIPS32 4KE family of synthesisable processor cores. The MIPS core family will be incorporated in the industry's leading IP library from Synopsys.
The DesignWare library is being expanded to provide designers with a complete, easy-to-use MIPS-based SoC design environment on their desktops.
In addition to the 4KE family of low-power synthesisable cores, the library contains an array of popular, preverified peripheral IP blocks that are easily connected to the MIPS Technology cores using the DesignWare AMBA-based microprocessor sub-system.
The complete package can then be used as the basis for SoC design with a high degree of confidence of obtaining working first-pass silicon.
"The top three design challenges hardware engineers face with microprocessors is finding IP that is easy to access, easy to evaluate and easy to implement", said Kevin Meyer, vice president of marketing at MIPS Technologies.
"By collaborating with Synopsys to help solve these critical systems issues, we bring the power of the industry-standard MIPS architecture to designers' desktops.
This is another key step forward in achieving 'right first-time' design".
The 4KE family of processor cores not only delivers 1.4 dhrystone MIPS/MHz of performance, but also provides many configurable options that allow the designer to optimise the core for their application resulting in increased performance while reducing die size and power consumption and, ultimately, total system cost.
The MIPS32 4KE family of cores consists of the 4KEc, 4KEm and 4KEp configurations.
The 4KEc has been designed for use in cost-sensitive digital consumer applications and contains a memory management unit for supporting multi-processing operating systems.
The 4KEm is equipped with a single-cycle multiply-accumulate unit for efficient execution in broadband access systems.
The 4KEp is used in a variety of low-power performance communications applications such as highly integrated networking cards and mobile devices.
Features such as 128Kbyte of cache and a coprocessor interface allow users to easily configure a 4KE core to maximise performance in their SoC applications.
MIPS16e code compression can reduce memory requirements by up to 40%, further reducing system costs, and extensive clock gating significantly reduces power consumption.
The cores' real-time trace capability supports software development and debugging with the industry's most popular tool chains.
Design views for the MIPS core family, used to perform design, simulation and verification, will be available to DesignWare licensees as part of the DesignWare Star IP program.
Full implementation views, including RTL, will be available for licensing from MIPS Technologies and delivered by Synopsys.
Design and implementation support will be provided by Synopsys.
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