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Product category: Intellectual Property Cores
News Release from: M2000 | Subject: FlexEOS
Edited by the Electronicstalk Editorial Team on 1 June 2004

IP embeds FPGA functions on ASICs

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FlexEOS embedded FPGA technology from M2000 has been successfully manufactured on a test chip in CMOS 130nm technology

This means that a "silicon-proven" FPGA macro is now available to ASIC designers who want to add "on-silicon" logic programmability to a design. Many fields of application can benefit from FlexEOS technology, including wireless infrastructure equipment, security, printers, automotive, set-top-boxes, HDTV and imaging.

"FlexEOS embedded FPGA macros use proprietary developments of the latest technology to achieve architectural density which is design-proven", said Gabriele Pulini, Vice President for Marketing and Sales at M2000.

He went on to add: "Among the major benefits that FlexEOS cores bring to ASIC design, one of the first is competitive advantage by making products flexible".

"Designers can now change the logic functions of an ASIC, or add new ones, using simple software tools".

"Secondly, a single platform ASIC can now be designed to support future product evolutions with no additional NRE investment".

Frederic Reblewski, President and cofounder of M2000, remarked: "FlexEOS uses an innovative architecture designed for full and fast reprogrammability".

"Its high density gives optimised silicon area, low consumption and high speed".

"The I/O interfaces are completely flexible".

He also insisted: "An efficient and flexible software flow is as important as optimised hardware architecture, both when integrating the macro on silicon, and also when customising the macro in a specific application environment".

"FlexEOS macros come with a state-of-the-art software tool suite for rapid compilation of new applications which can then be dynamically loaded into the FlexEOS core".

FlexEOS cores are hard macros available in different sizes, and which are portable to any silicon technology.

Their logic consists of an array of SRAM-based multi function logic cells (MFCs), reprogrammable structures which contain a four-input look-up table (LUT) and a flip-flop.

A multilevel routing hierarchy interconnects the MFCs.

All the core I/Os are symmetrical so that a predefined I/O placement is never a constraint when mapping a new function.

Any input can be used as a clock input, which allows multiple independent clock domains.

As an example, a FlexEOS core comprising 3072 MFCs represents the equivalent of approximately 30,000 ASIC gates.

Such a core has a size of 4.5mm2 in 130nm technology, and a configuration file of 28Kbyte which can be loaded in 0.5ms at 100MHz.

The maximum measured speed of this core is 700MHz.

The FlexEOS software flow is fully automatic, efficient and rapid, and is designed to interface with popular ASIC design flows.

Users can quickly and easily map a design to the core, and generate a simulation and timing model for full system verification.

The FlexEOS business model is based on a licence fee and royalties related to the production volume and type of macro.

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