Core family offers
full PCI Express solution
LSI Logic Corp has released a complete PCI Express solution, including serdes, pipe, datalink and transaction layer cores for RapidChip platform ASIC designs
The PCI Express family of cores is validated for functionality and interoperability and is compliant to the PCI Express standard. LSI Logic is currently engaged with multiple customers in PCI Express-based RapidChip Xtreme designs in 4-, 8- and 16-lane configurations. LSI Logic's RapidChip PCI Express cores are based on the company's highly successful cell-based ASIC cores that are proven in silicon, flexible and easy-to-implement.
Both the RapidChip Platform ASIC and cell-based cores showcase the company's physical layer (PHY) and serial protocols expertise.
"By offering a complete solution, LSI Logic greatly reduces PCI Express-based IC development and allows customers to focus on the value proposition of their architecture", said Jean Bou-Farhat, Vice President, LSI Logic.
"With PCI Express on our RapidChip platform ASICs, customers can realise unprecedented time to market at a low cost and with a predictable outcome".
LSI Logic's industry proven and PCI Express compliant GigaBlaze serdes cores are at the heart of the company's PCI Express offering, providing a full-duplex, point-to-point communication channel.
When using GigaBlaze cores, customers benefit from five technology generations of serdes deployment experience.
GigaBlaze cores in various RapidChip slices support multiple 1, 2, 4, 8 and 16 PCI Express lane configurations.
LSI Logic's link and transaction layer cores provide the physical/logical, data link and transaction functionality of the PCI Express standard.
These highly optimised and interoperable cores are architected to operate at 250MHz, offering high performance and low latency while supporting a rich set of features such as lane reversal, power management and flow control.
Developed by a team with extensive serial protocol design experience, LSI Logic's PCI Express link cores can save customers many man-years of design and verification time while ensuring right first time silicon.
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