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Product category: Intellectual Property Cores
News Release from: LSI Europe | Subject: DDR-2 cores and SSTL18 I/O
Edited by the Electronicstalk Editorial Team on 2 June 2004

Cores speed interface to DDR-2 memory

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A new physical layer memory interface aims to save customers months of development time while improving product performance with the industry's highest speed DDR-2 SDRAM technology

LSI Logic's new DDR-2 ASIC core is the first physical layer interface and I/O buffer to support 333MHz, 667Mbit/s data speeds, enabling manufacturers of data storage, communications, multifunction printers, industrial and medical equipment to take advantage of the memory technology's superior density, bandwidth and lower cost.

LSI Logic's DDR-2 core with SSTL18 I/O interface buffer can be quickly and easily integrated with a customer's own logic for fast SoC designs.

The DDR-2 is a preverified interface validated in silicon, significantly reducing the turnaround time and risk of chip development.

"LSI Logic has been highly successful with two generations of memory interface cores", said Jean Bou-Farhat, Vice President, CoreWare Division, LSI Logic Corp.

"The DDR-2 cores allow our customers to take advantage of the performance and cost benefits offered by DDR-2 SDRAM memory products".

"This new addition to the CoreWare library, combined with existing connectivity solutions, helps our customers design systems efficiently and quickly while also reducing risk".

LSI Logic's DDR-2 physical layer interface with preverified functionality, layout and timing closure combined with silicon validation, significantly reduces the risk and turnaround time of chip development.

The SSTL18 I/O buffer, with features including on-die termination (ODT), impedance controlled driver, and precision duty cycle matching, provide an electrical interface of superior signal integrity ensuring optimal performance and first pass success.

The DDR-2 cores and SSTL18 I/O are immediately available for customer design-ins and are easy to integrate into an ASIC design.

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