Core interfaces SoCs with DDR SDRAM
The LSI Logic DDR core, which greatly simplifies ASIC design for interfaces to DDR SDRAM, reaches datarates up to 400Mbit/s per pin at 200MHz
This innovative, easy-to-integrate core reduces development time and design complexities. The DDR cores are ideally suited for storage, computing, printer and communications applications. "Without the LSI Logic DDR core, an ASIC designer must design an interface that meets the tight timing requirements of DDR SDRAM, a challenging, time-consuming and costly effort.
By using this predefined and pre-verified core, our customers will realise shorter development times, lower system costs and greater performance and reliability", stated Dave Jones, vice president and general manager of LSI Logic's Storage and Computing ASIC Division.
"Demand is high for reliable interfaces between ASICs and high-speed DDR SDRAM.
LSI Logic is delivering this valuable technology today, and we'll continue to offer next generation cores as customer needs evolve".
"LSI Logic provided HP with a complete, preverified DDR core that handled the critical timing in our ASIC DRAM interface", said Rick Klaus, Senior Design Engineer, HP Imaging and Printing Group.
"This enabled us to more rapidly complete our memory controller design".
The LSI Logic DDR interface core is available in the company's G12 0.18-micron and Gflx 0.11-micron process technologies, leveraging LSI Logic's extensive expertise in high performance I/O interfaces.
The core provides a robust physical layer interface to high performance DDR SDRAM memory and uses a simple ASIC side interface.
The ASIC designer has the flexibility to use a performance-optimised DDR memory controller from LSI Logic, an internal memory controller or a third party memory controller.
"The G12 DDR core has been fully characterised with test chips and in several of our customer's products, meeting the 200MHz specification with plenty of margin", said Khanh Le, Vice President of High Speed Interface Engineering at LSI Logic.
The DDR SDRAM core is offered as a hardmac with preverified layout and timing.
The 8bit-wide core can be used in parallel to scale up to 32bit, 64bit and higher bus widths, giving designers the greatest flexibility.
Based on today's industry standards, the core allows designers to read and write DDR SDRAM memories in point-to-point and dual in-line memory module (DIMM) configurations.
The DDR cores are part of the LSI Logic CoreWare design program, an extensive library of pre-designed and pre-verified cores that can be easily integrated with customer-designed logic.
The CoreWare program reduces development time and overall system cost while increasing system performance and reliability.
Customer designs with the LSI Logic DDR cores are already underway.
The DDR interface core is also available in LSI's recently announced RapidChip semiconductor platform for fast SoC designs.
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