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News Release from: Ignios
Subject: SystemWeaver
Edited by the Electronicstalk Editorial Team on 15 June 2005

IP core manages ARC multiprocessing

A new electronic system level model demonstrates the seamless integration of multiple ARC family 600 cores, using Ignios SystemWeaver multicore-enabling technology.

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Ignios has unveiled an electronic system level (ESL) model that demonstrates the seamless integration of multiple ARC family 600 cores, using Ignios SystemWeaver multicore-enabling technology. The multicore SoC demonstration is based on 32 processors from the ARC 600 core family integrated with the SystemWeaver multicore-management IP core, which enables a high-level approach to software development for multicore SoC implementations. The demonstration shows that code which uses the SystemWeaver multithreaded API can be easily developed for a single ARC processor and then simply retargeted to a multicore implementation, with no need to recompile the source code.

The SystemWeaver IP core provides the flexible run-time management resources to co-ordinate the multiple processors to ensure that the system achieves efficient performance and power results.

SystemWeaver also provides nonintrusive access to trace information to enhance system-level debug for multicore configurations.

'An increasing number of ARC customers are implementing multiple cores on SoCs targeted at compute-intensive applications', commented Karl Auker, Director of Strategic Alliances at ARC International.

'By working with partners such as Ignios, ARC's licensees will have access to technologies that can ease the process of multicore software development and debug'.

'We are pleased with the work that Ignios has done in building this demonstration'.

'Working with ARC to demonstrate our SystemWeaver technology is another strategic milestone for Ignios', declared Rick Clucas, Ignios CEO.

'By demonstrating the support for ARC's patented industry-leading configurable processor architectures, we are confirming our position as a supplier of enabling technology for the next-generation of multicore SoCs'.

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