PCI Express core works with Rambus PHY
GDA Technologies has successfully completed of PCI-SIG compliance and interoperability testing of its PCI Express intellectual property (IP) GPEX core with the Rambus PCI Express PHY
GDA Technologies has successfully completed of PCI-SIG compliance and interoperability testing of its PCI Express intellectual property (IP) GPEX core with the Rambus PCI Express PHY, a complete serial communication cell optimised for implementing the physical layer of the PCI Express standard.
The joint test platform was demonstrated at the Intel Developer Forum in March 2005 in San Francisco.
'GDA PCI Express cores have been passing PCI-SIG compliance testing since December 2003 and have been proven interoperable with more than 20 systems', says Abhijit Sarid, Director of IP Marketing at GDA.
'With the inclusion of Rambus PHY implementation, our entries in the integrators list now cover a wider range of configurations and target technologies'.
'This reinforces our leadership position in PCI Express' digital core market'.
'The combination of GDA's most complete digital controller offering and Rambus' comprehensive PHY portfolio provides chip developers access to the broadest array of proven, interoperable PCI Express solutions, enabling fully compliant system products', said Jean-Marc Patenaude, Director of Marketing at Rambus.
The GDA PCI Express IP solution passed the entire test criteria set forth at the PCI-SIG compliance workshops, including protocol, electrical, and configuration tests, and submitted a completed PCI-SIG compliance checklist.
The PCI-SIG is the special interest group that owns and manages PCI specifications as open industry standards.
The organisation defines and implements new industry standard input/output (I/O) specifications as the industry's local I/O needs evolve.
'We are elated to announce interoperability with the Industry leading PHY solution', said Prakash Bare, Vice President of IP Business Unit at GDA.
'Rambus' extensive experience in the development of high volume, high speed I/Os combined with their impressive track record for PCI Express compliance and interoperability offers a highly dependable PHY option to our COT customers'.
The GDA PCI Express (GPEX) IP family is the most comprehensive solution available today for implementing PCI Express I/O in COT, as well as ASIC, FPGA and structured ASIC designs.
The highly configurable solution offers optimum area, power, timing, latency, bandwidth and ease of integration for a wide range of applications.
GPEX supports endpoint, root complex, switch and bridge implementations with all the possible link widths, virtual channels, functions and packet sizes specified in the PCI Express specification.
Line side interface is designed for interoperating with a wide range of PHY designs.
Several interface options are offered on the system side to cover all major application scenarios.
GPEX is exhaustively verified in simulation as well as silicon interoperating with most of the available third party simulation models, silicon implementations and systems.
The Rambus PCI Express PHY is a member of the Rambus Raser family of serial link interfaces.
The portfolio of PCI Express PHY cells is silicon-proven on multiple foundry and captive processes at every process node ranging from 180 to 65nm.
Rambus customers are shipping graphics, chipset, switch and bridge chips for applications using the PCI Express standard.
Rambus has also demonstrated its Turbo PCI Express platform with serial links operating at 5-6.4Gbit/s datarates to meet future PCI Express requirements.
In addition, Rambus offers its customers engineering services for chip integration, package, board and system characterisation and tests to ensure the successful development of PCI Express-based chips and systems.
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