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GDA Technologies has joined the LSI Logic RapidChip Partner Programme to deliver quality IP solutions. The RapidChip Partner Programme offers customers ready-to-use, fully verified and best-in-class products and services to develop advanced, next-generation technologies. "GDA is elated to be associated with the LSI Logic RapidChip Partner Programme".
"The ability of the RapidChip platform to deliver a low latency, high system performance, low risk path for building multigigabit serial interface designs along with the faster time-to-market at affordable NRE cost shall greatly benefit our IP customers?, said Prakash Bare, Vice President of IP Business at GDA Technologies.
"We strive to deliver quality IP solutions and take pride in LSI Logic's selection of our IP cores for their RapidChip platform ASICs".
"GDA is a proven supplier of high quality, compliant and interoperable high speed interconnect IP such as PCI Express, HyperTransport, RapidIO, Advanced Switching, Gigabit Ethernet, SPI4 and we are pleased to offer GDA IP to our RapidChip customers", said Ronnie Vasishta, Vice President of Technology Marketing at LSI Logic.
"RapidChip customers can easily integrate their design functionality with GDA IP and with LSI Logic's industry-compliant high-speed serdes and embedded standard processors, prebuilt on a RapidChip slice".
The RapidChip semiconductor platform combines the high-density, high-performance benefits of cell-based ASICs with the fast time-to-market and customisation benefits of FPGAs, and the proven IP benefits of ASSPs.
Targeting the communications, consumer, storage and other markets, RapidChip platform ASICs use LSI Logic's high-performance field-tested CoreWare IP, customisable logic, embedded memory, and innovative design concepts to significantly reduce design and manufacturing risk and costs.
RapidChip platform ASICs also provide a fast and seamless migration path to full standard-cell ASIC driving unit costs even lower.
Unique to RapidChip Platform ASICs is the customer-friendly interface that dramatically simplifies the underlying complexity of the design tools and flows associated with SoC design.
Rule sets automatically manage architectural design, verification and physical design.
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