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Product category: Intellectual Property Cores
News Release from: GDA Technologies | Subject: PCI-Xactor
Edited by the Electronicstalk Editorial Team on 24 September 2003

IP verifies PCI Express designs

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GDA Technologies has enhanced its PCI Express IP family by offering PCI-Xactor from Avery Design Systems

PCI-Xactor is a comprehensive PCI Express verification IP solution for endpoint, root complex, switch and bridge designs that will be included in GDA's PCI Express IP core offerings. GPEX, the first PCI Express IP from GDA includes the PCI-Xactor verification solution. The PCI-Xactor is also available as stand alone product through GDA.

"GDA's complete PCI Express IP solutions empower designers to implement exciting and innovative PCI Express-compliant products while significantly reducing design risks and verification time", said Prakash Bare, Vice President of IP Business at GDA Technologies "Avery's verification IP forms an important component of our PCI Express offerings.

We are pleased to be working with Avery team to provide our PCI Express customers unparallel quality and robustness in verification front".

"GDA is a proven IP supplier and Avery is pleased to partner with GDA to streamline PCI Express IP implementation for our customers", said Chris Browy, Vice President of Marketing at Avery Design Systems.

"Together the companies will develop an integrated solution addressing PCI Express Endpoint, Root Complex, and Switch/Bridge implementations.

Support for wide range of system topologies and PCI protocols enable customers to speed up compliance verification of GDA-based PCI Express designs".

The GDA PCI Express endpoint IP core, called GPEX adheres to the PCI Express 1.0a specifications and is available for both ASIC and FPGA implementations.

It supports endpoint, bridge, switch and root complex solutions.

It includes MAC, data link and transaction layers.

GPEX supports PIPE based PHY architecture and provides a flexible packet oriented user logic interface with an optional DMA controller.

GPEX configurable options include number of lanes (up to 16), number of virtual channels (up to eight), maximum payload size (up to 4Kbyte), and transmit retry/receive buffer size.

GPEX provides flow control support for both directions and completely handles PCI Express ordering rules.

The PCI-Xactor verification IP solution provides Verilog-based BFMs, transaction generation and protocol analyser functions, checklist coverage, and a functional compliance test suite including test coverage.

The functional compliance test suite is based on Intel and PCI SIG test specifications.

The bus exerciser provides a PCI transaction API for the generation of directed and random bus traffic.

The PCI-Xactor endpoint solution supports multiple root complexes and endpoints BFMs.

The PCI- Xactor switch/bridge solution supports a switch BFM and a multilink protocol analyser to verification transaction ordering and completion rules.

BFMs can be programmed to generate transactions or completions with normal or exceptional behaviours using over 20 different TL/DLL/PHY parameters.

GDA and Avery Design Systems are members of the Intel Developer Network for PCI Express Architecture and PCISIG.

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