News Release from: Carbon Design Systems
Edited by the Electronicstalk Editorial Team on 21 April 2004
Package accelerates verification regression
New enhancements to DesignPlayer will allow it to be seamlessly plugged into hardware regression environments, be driven by a variety of testbenches, and provide a 10x or greater performance gain.
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New enhancements to the DesignPlayer software package will allow it to be seamlessly plugged into hardware regression environments, be driven by a variety of testbenches, and provide a 10x or greater performance gain over current solutions. "Carbon's technology improved our regression performance by a factor of 10x over current simulators", commented Michael Shiuan, VP of Engineering at S3 Graphics. DesignPlayer improves regression performance for verification environments, which may include standard testbenches such as: Vera, Verisity, transaction-level, behavioural Verilog, C, C++ and SystemC.
In addition, DesignPlayer adds interoperability with popular simulators including those from Cadence and Synopsys.
"With this release, Carbon is building on its fundamental values of performance, accuracy, and broad applicability", said Steve Butler, President and Chief Executive Officer at Carbon.
"Carbon can now be used across the board for early stage hardware regression, pre-silicon software validation, and complete system validation".
Carbon's DesignPlayer is a cycle and register accurate runtime model of a chip or IP (intellectual property) core compiled directly from RTL.
Software drivers, diagnostics, and firmware can be validated up to 50x faster on Carbon's DesignPlayer engine compared with an event-based simulator.
Carbon's new release extends DesignPlayer into hardware verification regression environments in multiple ways.
Engineers that apply behavioural Verilog, Vera, or Verisity-based testbenches in a simulation regression environment improve their performance by simply plugging in an optimised DesignPlayer to replace their RTL model.
This release allows DesignPlayer engines to plug-and-play with popular simulators including Cadence Incisive and Synopsys VCS.
Verification teams using DesignPlayer with C, C++, or transaction-level testbenches (without a simulator) can achieve a 10-20x regression performance boost over RTL simulation, while maintaining cycle and register accuracy.
Designers that use SystemC to simulate fast abstract models of their design early in the development cycle, face a daunting simulation performance problem as RTL implementation models are substituted for their abstract counterparts.
Simulation performance-when it's needed most-drops tremendously.
DesignPlayer now sports an automatically generated SystemC interface to allow it to be instantiated in a SystemC environment and provide an immediate 10-20x performance increase, without losing accuracy.
Carbon's DesignPlayer products are shipping now with pricing based on an annual subscription volume model.
DesignPlayer engines used for development are under $10,000 per seat for high volume purchases, and IP distribution versions approach $1000 per seat.
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