TSMC adopts Rubix for hardening CPU cores
Azuro has announced that TSMC has adopted its Rubix clock concurrent optimisation capability for hardening of embedded CPU cores.
Rubix increases clock frequency and reduces leakage power on our hardened CPU cores, and it does this without any change in sign-off methodology.
At advanced process nodes, rising on-chip variation and rising clock latencies are causing design timing to diverge after clock tree synthesis, even if tight skews are achieved.
Clock concurrent optimisation is said to be a new approach to clock tree synthesis (CTS), which builds clocks directly to deliver the best timing and power rather than simply to deliver tight skews.
Since the clocks are also built concurrently with logic sizing and placement, efficient global trade-offs can be made between fixing timing problems with clock skew and fixing timing problems with logic sizing or placement.
Not what you're looking for? Search the site.
- Spyglass-CDC reduces SoC design risks
- Kongsberg selects Integrity for missile programme
- IAR enables medical-alert system development
- Mediatek selects Jivaro netlist reduction platform
- Software library created for NXP microcontrollers
Request your free weekly copy of the Electronicstalk email newsletter ...
Browse by category
- Active components (13499)
- Passive components (3575)
- Design and development (10240)
- Enclosures and panel products (3956)
- Interconnection (3619)
- Electronics manufacturing, packaging (3477)
- Industry news (2104)
- Optoelectronics (1953)
- Power supplies (2989)
- Subassemblies (5605)
- Test and measurement (5770)