Axys aids ARC development
ARC has licensed Axys Design's MaxCore and MaxSim Developer Suites to develop, package and distribute processor models for the new ARCtangent-A5 microprocessor
ARC has licensed Axys Design's MaxCore and MaxSim Developer Suites to develop, package and distribute processor models for the new ARCtangent-A5 microprocessor, a user-customisable 32bit RISC core for ASIC, SoC and FPGA integration. Under the multiyear agreement, Axys Design will supply development tool suites to ARC's architecture and model development teams.
The tools extend the flexibility already offered by the synthesisable, configurable, and extendable ARCtangent-A5 architecture by enabling the creation of processor models that can be used -alone, or integrated into third party simulation or hardware/software cosimulation tools.
The models will also be integrated with ARC's MetaWare High C/C++ tool suite and the task-aware SeeCode debugger.
Farzad Zarrinfar, SVP of marketing and business development for ARC International, said, "After an extensive evaluation, we chose MaxCore and MaxSim to create very fast, reliable and accurate models for our processor that our customers can use for effective development of complex embedded SoCs.
Our goal to become the leader in integrated embedded system solutions requires the use of best in class tools to satisfy the sophisticated needs of our customers.
Axys Design's tools and technical support more than met our expectations and in combination with their attractive technology roadmap provide the right solution for our processor modelling needs".
An important aspect is that the modelling tools needed to support ARC's user-reconfigurable architecture.
MaxCore offers various features to support user configurability at the core level, including a model API that allows the addition of customer specific instructions.
MaxCore can generate instruction-, cycle- or fully pipeline-accurate processor models to address varying needs throughout the SoC development cycle.
While instruction accurate models provide maximum performance for early software development, SoC integrators and embedded software developers need more accurate models to verify the architecture and to cosimulate software against the actual chip design.
"As the leader in user-customisable processors and software for communications and consumer products, ARC International is dedicated to offer its customers the best cores, software and tools in a complete package.
We are extremely pleased that ARC chose MaxCore and MaxSim to complement and extend their unique offering of system-on-chip solutions", said Vojin Zivojnovic, president and CEO of Axys Design.
MaxCore generated processor models support the MaxSim component API as native interface but can also be used -alone or integrated with other tools.
MaxSim allows the rapid extension of a model beyond the actual processor core to the processor subsystem, including components such as caches, memory management and interrupt control, while preserving full cycle-accuracy where necessary.
In addition, MaxSim allows the creation of complete application-specific multicore platform models that can be used as virtual reference platforms to enable early architecture exploration and embedded software development.
MaxSim provides powerful debug features including memory and register windows and supports a variety of ard debuggers through its unique debug server, enabling fully synchronous multiprocessor debugging using heterogeneous processors and debuggers.
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