IP puts SoCs on the PCIbus
Eureka Technology is to make available the plug-in IP modules it developed for the ARCtangent processor to connect to memory devices and the PCIbus
Eureka has already delivered ARC-processor-based solutions to Fujitsu Microelectronics America earlier this year. Adding a PCI interface is a significant step as it takes processor connectivity from the SoC level to board level. This adds an extra interface capability to the ARCtangent processor, enabling single-chip PCI solutions suitable for high-bandwidth applications requiring the high performance PCI specification 2.2 protocol.
Eureka Technology provides two IP cores for the ARCtangent processor.
The EP503 memory and peripheral controller interfaces between the processor's arbitration unit and provides access to external SDRAM, Flash, and PCI host bridge and peripheral slave devices.
The EP453 PCI host bridge contains bus master, bus target, and configuration initiator function, to support instruction transfer in both directions allowing an ARCtangent processor core to access devices on the PCI (specification 2.2 protocol) bus and allows a remote PCI bus master to access the system internal resources through the client interface and memory arbitration units.
The EP503 memory controller is optimised to serve as the slave device for the ARCtangent bus arbitration unit.
The memory controller automatically handles SDRAM and Flash timing such as row and column latency, precharge timing, and data burst length.
All these timing parameters are set by the memory controller on system reset and can be programmed by the user during run-time to optimise system performance.
The EP503 supports all industrial standard SDRAM organisations, ranging from 16 to 256Mbit devices, and from X4 to X32 data width.
Data bandwidth between the Flash devices is programmable through read/write access time parameters in the memory controller.
Interfacing to user-defined slave devices is through a user-friendly interface from the EP503.
Access timing to the slave device is programmable.
Address and data bus can be shared among all memory and slave devices.
The EP503 is designed to support external SDRAM and Flash while the slave device and PCI host bridge can be either on-chip or off-chip.
The EP453 fully supports the PCI specification 2.2 protocol, and is designed for ASIC and FPGA implementations in various system environments.
It is a bus interface unit designed for efficient interface between the ARCtangent processor and the PCI bus, performing all the data transfer functions necessary for the bus mastering device to access data through the PCI bus.
It supports burst data transfer to maximise data bandwidth.
The target function allows other PCI masters to access internal system resources.
It supports high-speed bus request and arbitration to minimise transfer latency.
The host bridge operates in two clock domains, the CPU bus clock and the PCI bus clock - the two clock domains can be asynchronous to each other.
Single and burst data transfers are supported both as bus master and bus target.
The EP503 interfaces directly to the ARCtangent peripheral controller to provide access by the CPU core.
The host bridge core allows the CPU to initialise the entire system during power-up reset using standard PCI protocol.
Functionality of both IP cores has been fully verified on simulation and demonstrated in silicon.
They are available for licensing directly from Eureka Technology.
Customers can purchase a full license for the ARCtangent processor that includes the core configuration utilities, development tools and the ARCangel prototyping system directly from ARC Cores.
Integration of the ARCtangent processor can be carried out by any of ARC's worldwide network of design centres.
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