Novel architecture mixes 16 and 32bit instructions
ARCompact is an innovative instruction set architecture (ISA) from ARC Cores that allows designers to mix 16 and 32bit instructions on its 32bit user-configurable processor.
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ARCompact is an innovative instruction set architecture (ISA) from ARC Cores that allows designers to mix 16 and 32bit instructions on its 32bit user-configurable processor. The key benefit of the ISA is the ability to cut memory requirements on an SoC by up to 30%, resulting in lower power consumption and lower cost devices in deeply embedded applications such as wireless communications and high volume consumer electronics products. The main features of the ARCompact ISA include new 32bit instructions aimed at providing better code density, a new set of 16bit instructions for the most commonly used operations, and freeform mixing of 16 and 32bit instructions without a mode switch - significant because it reduces the complexity of compiler usage compared to competing mode-switching architectures.
Phil Barnard, product manager responsible for ARCompact said, "The new instruction set expands the number of custom extension instructions that customers can add to the base-case ARCtangent processor instruction set.
The existing processor architecture already allows customers to add as many as 69 new instructions to speed up critical routines and algorithms.
With the new ISA, customers can add as many as 256 new instructions.
As before, customers can also add new core registers, auxiliary registers, and condition codes.
The ARCompact ISA thus maintains and expands the user-customisable features of ARC's configurable processor technology".
Barnard comments, "As 32bit architectures become more widely used in deeply embedded systems, code density can have a direct impact on system cost.
Typically up to 90% of the silicon area of a system-on-chip is taken up by memory".
The ARCompact ISA delivers high density code helping to significantly reduce the memory required for the embedded application, a vital factor for high-volume consumer applications, such as flash memory cards.
In addition, by fitting code into a smaller memory area, the processor potentially has to make fewer memory accesses.
Finally, the new, shorter instructions can improve system throughput by executing in a single clock cycle some operations previously requiring two or more instructions.
This can boost application performance without having to run the processor at higher clock frequencies - a capability already utilized by ARC's existing customers.
The support for freeform use of 16 and 32bit instructions allows compilers and programmers to use the most suitable instructions for a given task, without any need for specific code partitioning or system mode management.
Direct replacement of 32bit instructions with new 16bit instructions provides an immediate code density benefit, which can be realised at an individual instruction level throughout the application.
As the compiler is not required to restructure the code, greater scope for optimisations is provided, over a larger range of instructions.
Application debugging is more intuitive because the newly generated code follows the structure of the original source code.
The new ISA will first become available with the release of the ARCtangent-A5 processor in Q4 2001.
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