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News Release from: ARM | Subject: Velocity DDR memory interface products
Edited by the Electronicstalk Editorial Team on 21 July 2006

Memory interface IP makes
more of embedded DDR

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ARM has expanded its Velocity DDR memory interface products to support a number of application-specific SDRAM requirements

ARM has expanded its Velocity DDR memory interface products, part of its Artisan physical IP family, to support a number of application-specific SDRAM requirements. The expanded ARM Velocity DDR products are compliant with JEDEC standards for DDR, DDR2, Mobile DDR and GDDR3 SDRAM and support standard CMOS processes on 130, 110, 90 and 65nm nodes for leading foundries.

The ARM Velocity portfolio targets applications in mainstream PC and server with datarate speeds up to 800Mbit/s.

Velocity Mobile DDR solutions target low-power applications while GDDR3 solutions target graphics memory interfaces up to1600Mbit/s datarate.

The Velocity DDR solutions are designed to be smaller with lower jitter performance than previous products, which continue to enable customers to optimise power and size in their SoC designs, while reducing time to market.

'ARM DDR products reduce risk for us when developing our complex IP and play a vital role in Azul's overall SoC design, as all of our interfaces and clock generation IP are developed by ARM', said Paul Koike, Senior Director, Silicon Engineering, Azul Systems.

'As we continue to move our designs to smaller geometries, we believe that ARM provides the most complete line of interconnect I/O IP for 90nm'.

Complexity and higher-speed memories are demanding a different approach from the pure digital methods used in the past.

Currently there is a greater need for a mixed-signal solution to address issues such as signal and voltage integrity and impedance discontinuities.

ARM silicon-proven expanded Velocity DDR solutions have added on-die termination for programmable termination to improve signal integrity and have advanced dynamic calibration, with higher DDR2 resolution of the input and output impedances, ensuring more accurate impedance matching.

Along with these enhancements to previous DDR products, the Velocity DDR solutions are also easily integrated cells that allow designers to optimise power, size and jitter performance in each design, reducing overall systems costs.

'SoC designers are looking for IP solutions that help reduce risks, enable seamless integration and speed design development', said Neal Carney, Vice President of Marketing, Physical IP, ARM.

'By providing silicon-proven industry-standard DDR memory interface solutions, ARM facilitates faster time to market for our customers and enables them to remain competitive in their SoC space'.

The ARM expanded Velocity DDR solutions also include a comprehensive, speed-graded portfolio of analogue timing functions such as application-specific DLLs for centreing clocks in data eyes as well as timing of DDR.

In addition, application-specific PLLs are included to generate accurate DDR system clock signals.

ARM also offers a range of PrimeCell amba 3 AXI and Amba 2 AHB dynamic memory controllers supporting SDRAM, DDR and Mobile-DDR.

With DDR2 support under development, ARM now provides a complete, high-performance memory controller solution for a wide range of applications.

ARM Velocity DDR memory interfaces are immediately available in a variety of standard CMOS processes on 130, 110, 90 and 65nm nodes for leading foundries.

The ARM PrimeCell AXI static memory controller series and the ARM PrimeCell AHB memory controller series are also available for immediate licensing.

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