Clock and data recovery
ICs add margin for error
New clock and data recovery ICs simplify system design by exceeding Sonet jitter specifications in all categories by more than a factor of three
Analog Devices is extending its portfolio of clock and data recovery (CDR) integrated circuits (ICs) for networking applications with four new devices. For designers of datacomms and telecomms applications that require extra margin to increase robustness and ease interoperability issues, the new CDRs simplify system design by exceeding Sonet jitter specifications in all categories (jitter transfer, jitter generation and jitter tolerance) by more than a factor of three.
The ADN2817 and ADN2818 improve on ADI's leading family of continuous-tuning CDRs for networking applications by consuming up to 25% less power and offering more features than the previous generation.
In addition, ADI is introducing two ultra-low-power fixed-rate ICs that are pin-compatible with ADI's continuous tuning CDRs and are optimised to minimise the cost and complexity of implementing broadband PON (BPON).
The ADN2817 (650mW) and ADN2818 (600mW) are low-power extensions of ADI's family of pin-compatible continuous-tuning CDRs for fixed-rate, multirate and continuous-tuning data communications and telecom applications.
The ICs are capable of recovering continuous data at rates from 10Mbit/s to 2.7Gbit/s without external control or the use of a reference clock making these devices optimal for WDM systems that require protocol agnostic capability.
The ADN2817 and ADN2818 offer up to a 1.5dB improvement in optical sensitivity over the previous generation CDR.
Via an I2C interface, optional features can be accessed such as double datarate (DDR) that provides a half rate clock, datarate read back to identify the datarate of the incoming signal, and datarate provisioning that provides the ability to allow the device to only lock to one particular datarate.
The ADN2804 and ADN2806 are fixed-rate CDRs that deliver the low power, features and datarates to exceed BPON requirements.
The devices automatically lock to a 612Mbit/s input data stream without the use of a reference clock or external control.
Additionally, in the absence of input data, the devices are able to maintain an accurate output clock.
The ADN2804 includes an on-chip limiting amp and dissipates 423mW, whereas the ADN2806 has no limiting amp and dissipates only 35mW.
All four CDRs are packaged in 5 x 5mm LFCSPs (lead frame chip scale packages).
The ADN2817 and ADN2818 are sampling now, will be available in full production quantities in August 2006, and are priced at $43.74 and $41.55 per unit, respectively, in 1000-piece quantities.
The ADN2804 and ADN2806 are available in full production quantities now and are priced at $9.88 and $9.13, respectively, per unit in 1000-piece quantities.
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