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Product category: Programmable Logic Devices
News Release from: Actel Europe | Subject: Libero 6.3 software
Edited by the Electronicstalk Editorial Team on 09 November 2005

Secure design flow for complex FPGA
development

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The latest version of Libero 6.3 software provides a secure design flow for integrating Actel's CoreMP7, the soft ARM7 family processor, into Actel's non-volatile field-programmable gate arrays.

The latest version of Libero 6.3 software provides a secure design flow - from synthesis through implementation - for integrating Actel's CoreMP7, the industry's first soft ARM7 family processor, into Actel's single-chip, non-volatile field-programmable gate arrays (FPGAs) With this software release, Actel builds on the capabilities of its industry-leading SmartTime static timing analysis environment to deliver enhanced minimum-delay support, uniquely enabling precision hold-time characterisation for high-speed FPGAs

The enhanced software also automates the task of I/O voltage assignment and supports Actel's new RTAX4000S devices, the industry's highest density