IP deployment platform
eases FPGA design
The CoreConsole IP deployment platform has been developed to simplify the construction of FPGA-based system-level applications
Actel has released CoreConsole, an IP deployment platform (IDP) developed to simplify the construction of FPGA-based system-level applications. With CoreConsole, designers can quickly assemble the components of an FPGA-based design, including the system processor, configurable microprocessor subsystem and interconnect bus.
The tool will play an important role in facilitating the development of single-chip, Flash-based Actel FPGAs implementing CoreMP7, the company's new ARM7 family soft IP microprocessor.
By allowing users to focus on the system rather than individual components, the CoreConsole IDP enables early system-level evaluation and significantly reduces overall system development time.
'The rich feature set and easy-to-use graphical user interface of CoreConsole greatly eases implementation of Actel's CoreMP7 soft IP microprocessor in our FPGAs', said Yankin Tanurhan, Senior Director, Applications and IP Solutions at Actel.
'The development of this tool demonstrates Actel's commitment to advancing the use of the industry-leading ARM7 family technology within programmable logic devices and making FPGA-based system development obtainable for every designer'.
Use of Actel's CoreMP7 for system-level designs requires the implementation of a supporting subsystem around the microprocessor core.
Implementation of this subsystem, which includes interrupt controllers, memory controllers, timers, serial interfaces, I/O ports and power-on reset (POR) circuitry, can be a tedious and time-consuming process if done manually.
CoreConsole facilitates the implementation and configuration of the subsystem by automating the stitching of the components and allowing users to assemble the subsystem graphically at the function level, thus cutting development time from days to minutes.
Operating at the design-entry phase of the development process, CoreConsole is a bus-centric tool that automatically connects IP cores to the interconnect bus.
The tool includes a block stitcher that enables IP blocks, including user IP, to be easily stitched together into synthesisable and simulatable RTL that is usable in Actel's Libero integrated design environment (IDE).
Additionally, CoreConsole contains an IP vault that provides access to Actel's CoreMP7, the subsystem components and other IP that can be licensed from Actel's DirectCore portfolio, as well as third-party IP from Actel's CompanionCore partners.
CoreConsole is implemented at a level of abstraction above the RTL and is independent of the interconnect bus, processor, subsystem and IP blocks, enabling it to be used with different interconnect standards, future processor IP and a broad range of IP blocks.
Additionally, CoreConsole delivers all relevant IP software drivers to be used with the microprocessor software program development tools.
The CoreConsole tool's Windows user interface is graphical, intuitive and easy to use, supporting the instantiation and configuration of the processor subsystem functions, Actel DirectCores, Actel CompanionCores and user-defined IP blocks.
After the IP is stitched to the bus, the tool generates a system interconnect test bench that can be used to validate and debug the connection of the design within the FPGA fabric.
CoreConsole uses methods defined by the Structure for Packaging, Integrating and Re-using IP within Tool-flows (SPIRIT) initiative and includes underlying structures based on XML code, allowing designers to use their SPIRIT-compliant cores and ensuring the easy transfer of IP between vendors.
Pricing and The CoreConsole IDP tool is priced at $395 for a one-year licence and is available from Actel. Request a free brochure from Actel Europe....
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