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Product category: Programmable Logic Devices
News Release from: Actel Europe | Subject: Axcelerator design environment
Edited by the Electronicstalk Editorial Team on 04 November 2004

Faster timing closure with design
environment

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Actel's Libero Integrated Design Environment (IDE) offers strengthened support for the company's antifuse-based, single-chip Axcelerator field-programmable gate arrays (FPGAs).

Actel has announced that its Libero Integrated Design Environment (IDE) offers strengthened support for the company's antifuse-based, single-chip Axcelerator field-programmable gate arrays (FPGAs), extending significant improvements in silicon performance, quality of results (QoR) and timing closure to its Axcelerator customers Advancements made within timing-driven place and route, including a new predictive layout and routing technique that allows improved analysis of chip resources, result in an average of 10 percent improvement in Fmax and up to 15 percent improvement on the most complex designs

Additionally, enhancements made to the Mentor Graphics LeonardoSpectrum a