Flash-based FPGAs find a
home in the JSF
Actel Flash-based FPGAs have been chosen by Hamilton Sundstrand for the F-35 Joint Strike Fighter (JSF) project
Actel's single-chip, reprogrammable ProASIC Plus devices have been selected to manage the communication protocol in the fighter's engine control system and to serve as the interface to the engine's central processing unit. The ProASIC Plus family's reprogrammability facilitate rapid prototyping of the new high-speed communication protocol, and its nonvolatility and single-chip form factor enable engineers to meet the system's tight board-space constraints.
Hamilton Sundstrand has used Magma Design Automation's Palace physical synthesis tool for programmable logic devices, available as part of Actel's Libero integrated design environment (IDE), to create a more efficient design and achieve the highest performance for the ProASIC Plus FPGA solutions.
"The combination of reprogrammability and nonvolatility provided by Actel's ProASIC Plus FPGAs was critical in our selection process as we looked for a solution that allowed us to prototype quickly and would also take us through production".
"Design security and firm-error immunity were also strong considerations in the selection of an FPGA for this design", said Patrick J Sears, Senior FPGA design Engineer, ASIC Group, at Hamilton Sundstrand.
"Additionally, we were impressed by Palace and its ability to improve our overall design performance by as much as 50%".
Request a free brochure from Actel Europe....
? Actel Europe: contact details and other news
? Email this news to a colleague
? Register for the free Electronicstalk email newsletter
? Electronicstalk Home Page
Search the Pro-Talk network of sites