FPGA design environment
promises faster timing
Actel has enhanced its Libero integrated design environment (IDE) to provide customers with faster timing closure when using the company's Flash-based ProASIC Plus FPGAs
With tighter integration between the timer engine and timing-driven place and route, the Libero v5.2 IDE offers pushbutton results that often meet or exceed customer requirements, thereby reducing the number of design iterations required to achieve timing closure. Actel's Libero v5.2 IDE, together with the enhanced Magma Palace v1.1 physical synthesis software, enables designers using ProASIC Plus FPGAs to achieve an average performance boost of 20%.
Other new features of the Libero IDE include the addition of Actel's ChainBuilder software, which enables programming or testing of Actel's ProASIC Plus FPGAs when included in a daisy chain of devices, and support for the Linux Red Hat 7.1 platform for Actel's Designer physical design tool suite within the Libero IDE.
The tighter integration between the timer engine and timing-driven place and route gives higher priority to user constraints, increasing designer control over place and route to help converge on timing requirements.
Further, new improvements to Actel's routing algorithms also contribute to the performance improvements for ProASIC Plus devices.
Additionally, Magma's Palace physical synthesis software has also been enhanced to provide an additional 10 percent performance improvement on average for the ProASIC Plus devices.
Integrated with Actel's Libero IDE, the simple-to-use Palace tool accepts an interpreted netlist and makes optimised placement decisions based on constraints and detailed design and interconnect modelling.
In the past, developers have had to manually identify devices and their order within a chain.
Now, the Libero and Designer tool suites feature Actel's ChainBuilder software, which allows for the creation of a concatenated STAPL file from a graphical user interface.
A programmer, such as Actel's FlashPro, can then use the file to program or test a daisychain of FPGAs, custom ICs, microcontrollers and/or microprocessors.
Additionally, with ChainBuilder, specific Actel FPGAs can be isolated from other FPGAs, both Actel and non-Actel devices, and programmed individually or in parallel via a common header attached to the JTAG chain.
Companies are adopting Linux in an increasingly open-source world.
To broaden its platform support for its tool suites, Actel is now supporting Designer software on Linux Red Hat 7.1.
Actel plans to provide support for additional Linux platforms over the next year.
To improve ease of use and reduce development time, especially for designers who are less familiar with the Libero software, Actel has added a new project manager graphical interactive flow window to make the design flow more intuitive and provide a step-by-step guide through the design process.
Actel's Libero v5.2 IDE offers the latest and best-in-class tools from EDA partners Mentor Graphics, SynaptiCAD, Synplicity and Magma Design Automation, as well as custom developed tools from Actel, integrated into a single FPGA development package.
Actel offers one-stop shopping for its customer's EDA tool needs by means of a powerful design manager that keeps track of design files and seamlessly manages the interoperability issues that typically arise when using tools from different vendors.
The Actel Libero v5.2 IDE will be available in mid-February in four editions: Platinum PS (physical synthesis), Platinum, Gold and Silver.
Libero Silver may be used by qualified designers for one year free of charge via the Actel website.
Pricing for the Platinum PS version, including the Actel edition of Magma's Palace tool, begins at $3495 for a one-year licence.
An evaluation version of Libero Platinum PS may be used by qualified designers for 45 days free of charge.
Pricing for Libero Platinum and Libero Gold is $2495 and $595, respectively.
A one-year stand-alone licence for the Palace software for use with Actel's Designer is available from Actel for $1795.
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