FPGAs are radiation-tolerant
alternative to ASICs
Building on its continuing commitment to develop new high-reliability products for the aerospace community, Actel has unveiled its next-generation, radiation-tolerant RTAX-S FPGAs
Building on its continuing commitment to develop new high-reliability products for the aerospace community, Actel has unveiled its next-generation, radiation-tolerant RTAX-S field-programmable gate array (FPGA) offerings. With densities up to 2 million equivalent system gates (approximately 250,000 ASIC equivalent gates), the new space-optimised, high-density, single-chip devices offer key features, such as hardened registers that offer practical single-event upset (SEU) immunity and, for the first time, usable error-corrected onboard RAM.
These features position the RTAX-S family as the only viable radiation-tolerant alternative to application-specific integrated circuits (ASICs) that meets the density, performance and radiation-resistance requirements of many satellite applications.
Actel's RTAX-S devices will allow the company to aggressively target bus and payload applications in low-, mid- and geosynchronous-earth orbit satellites.
"In addition to breaking the 1-million gate barrier, Actel's new antifuse-based, radiation-tolerant RTAX-S FPGAs serve as another proof point in the company's long-standing commitment to delivering high-quality, radiation-tolerant solutions for space applications", said Barry Marsh, Vice President of Product Marketing at Actel.
"ASICs have traditionally been used to meet the high-density, high-performance requirements of payload applications in space.
We believe our high-density RTAX-S family not only meets the stringent demands of these applications, but offers tremendous advantages over ASICs, including increased flexibility, shortened design time and low-cost benefits".
The RTAX-S devices offer inherent single-event latchup (SEL) immunity; better than 37MeV-cm2/mg SEU capability; and total ionising dose (TID) performance in excess of 200krad.
The family also features embedded RAM with an upset rate of less than 1e-10 errors/bit-day with error detection and correction (EDAC).
With 2-million system gates, the largest device in the family, the RTAX2000S, contains support for up to 288Kbit of embedded SRAM; 684 user I/Os; and 10,752 SEU-hardened registers.
Based on Actel's AX architecture and scalable platform, the RTAX-S devices include several key architectural advancements: an embedded FIFO controller; a fully fracturable SuperCluster that allows high logic module usage; a core tile structure that provides tighter clock skew across the device; and a flexible clock structure with eight global clocks available equally across the chip, eliminating the need for clock floorplanning and easing design migration.
To complement the high densities and performance of the RTAX-S family, Actel offers a new MIL-STD-1553B bus controller intellectual property (IP) core, the company's second MIL-STD-1553B offering.
The Core1553BBC is a complete dual-redundant bus controller that CAN interface to standard external transceivers.
Actel's new bus controller solution provides low-power operation at 12, 16, 20 and 24MHz.
Delivering a complete solution, Actel provides everything needed to incorporate a 1553B bus controller into a system design, including an evaluation board, development tools, documentation and software.
To enable board-level functional verification and simulation of production-qualified solutions, Actel is offering RTAX-S prototyping capability via hardware adaptors that leverage the company's commercial Axcelerator FPGAs, which are also based on the AX architecture.
Additionally, Actel's RTAX-S prototyping solution includes software support for error detection and correction IP, which mitigates SEUs in the user memory.
Application notes explaining how to design RTAX-S-based applications using Axcelerator devices are available from Actel's website.
The RTAX-S family is supported by the Actel Libero integrated design environment and Actel Designer tool suite, which includes place and route, timing analysis and memory generation functionality.
Additional support for the family is provided by industry-leading third-party tools from Model Technology, Mentor Graphics, Synplicity, Cadence Design Systems and Synopsys.
Prototyping capability for the first members of the RTAX-S family, the RTAX1000S and RTAX2000S, which offer 1-million and 2-million equivalent system gates, respectively, is currently available with production scheduled to begin in 2H 2004.
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