Product category: Programmable Logic Devices
News Release from: Actel Europe | Subject: CompanionCore IP blocks
Edited by the Electronicstalk Editorial Team on 12 May 2003

Cores turn FPGAs to PowerPC interfacing

Eureka Technology has optimised three PowerPC interface IP cores for use with Actel's nonvolatile ProASIC Plus, Axcelerator, SX-A and RTSX-S FPGAs.

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Actel's latest CompanionCore Alliance programme partner, Eureka Technology, has optimised three PowerPC interface IP cores for use with nonvolatile ProASIC Plus, Axcelerator, SX-A and RTSX-S FPGAs. The combination of Actel's single-chip, nonvolatile FPGAs and Eureka's silicon-proven IP cores is ideal for communications, military, aerospace, medical, industrial and automotive systems using or connecting to PowerPC microprocessors. The three Eureka/Actel IP cores consist of the EP201 PowerPC bus master, the EP100 PowerPC bus slave and the EP300 PowerPC bus arbiter.

The cores not only support the PowerPC 603, 604, 740, 750 and 8260 bus interfaces, but also support several features of the PowerPC CPU device, including burst data transfers, data pipelining, extended data transfer sizes and support for multiple bus masters.

The CompanionCore IP blocks will serve as control blocks that, once embedded in an SX-A device (for example), allow designers to interface an Actel FPGA to a PowerPC-based system, rather than designing a custom interface on the FPGA to do so.

Optimised for Actel's FPGAs, the three PowerPC interface cores are available today in VHDL and Verilog RTL source code formats and EDIF netlist formats directly from Eureka Technology.

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