News Release from: Actel Europe
Edited by the Electronicstalk Editorial Team on 9 August 2002

Low-end device puts Flash FPGAs in consumer slots

A new low-cost lower-density device extends the appeal of the Actel ProASIC Plus field-programmable gate array family to the cost-sensitive, high-volume consumer market.

Note: A free brochure or catalogue is available from Actel Europe on the products in this news release. Click here to request a copy.

In a move that extends the reach of its reprogrammable, Flash-based ProASIC Plus field-programmable gate array (FPGA) family, Actel has introduced the 75,000-gate APA075, expanding the family to seven devices ranging in density from 75,000 to 1 million system gates. At the new density and sub-$8 price point, the APA075 device enables Actel to provide a suitable price/performance solution to the cost-sensitive, high-volume consumer market. The company has also unveiled its FlashLock on-chip security feature, which adds another level of design security to the company's Flash-based FPGA devices.

In addition, 20% performance improvements have been made possible by Actel's design tools, Actel Designer software and Actel Libero integrated design environment.

These security and performance improvements allow Actel to target a wider range of ASIC alternative applications.

These include set-top boxes, video games, network and telecom line cards, industrial controls, wireless networking, medical and avionics.

"The industry's acceptance of Actel's flash-based offerings has exceeded our expectations.

Since its introduction earlier this year, the ProASIC Plus solution has won an unprecedented number of design wins in multiple market segments, making it the fastest ramping family in Actel's history", said John East, president and chief executive officer at Actel.

"And now, with the new APA075 device, FlashLock security feature and 20% performance improvement derived from the Actel Designer and Actel Libero tools, we expect that a broader base of the design community will migrate to ProASIC Plus, especially in the cost-sensitive consumer arena".

As the complexity, capabilities and market share of FPGAs increase so does the need to secure the intellectual property implemented in FPGAs.

Nonvolatile Flash FPGAs, like Actel's ProASIC Plus family, offer levels of design security beyond conventional SRAM-based FPGAs and ASIC solutions.

Actel's ProASIC Plus FPGAs are user programmed with a key, ranging from 79 to 263bit, that blocks external attempts to read or alter the configuration settings.

Built from the ground up to offer enhanced design security, Actel has unveiled its on-chip security mechanism, called FlashLock, that enables designers to lock the design after programming to prevent unauthorised changes.

The FlashLock feature can also be used to thwart common security problems faced by designers using conventional SRAM devices, including overbuilding, cloning, reverse engineering and denial of service.

Design benchmarks show that the Actel Designer R1-2002 software, announced in June 2002, and Actel Libero integrated design environment deliver an average of 20% better performance on ProASIC Plus designs in a variety of customer applications.

This improvement was achieved through enhancements to the quadratic placer in the Actel Designer offering.

Integrated into the Actel Libero integrated design environment or used as a standalone tool suite, the Actel Designer software includes place-and-route, timing analysis and memory generation functionality to accelerate and automate the system design process without forcing the designer to relinquish control.

Actel's second-generation, reprogrammable, flash-based ProASIC Plus FPGA family delivers high performance with system speeds of up to 100MHz and allows designers to seamlessly interface between 3.3 and 2.5V devices in a mixed-voltage environment.

The family contains two advanced clock-conditioning blocks, each consisting of a phase-locked loop (PLL) core, delay lines and clock multiplier/dividers.

Additionally, two high-speed LVPECL differential input pairs accommodate clock or data inputs.

In-system programmability (ISP) is supported through the IEEE standard 1149.1 JTAG interface.

The single-chip, "live-at-power-up" APA075 device includes multiple PLLs and support for up to 27Kbit of two-port embedded SRAM and 158 user-configurable I/Os.

Sampling and production of the APA075 is scheduled to begin in Q3 2002.

Volume pricing for the new device is expected to be below $8 by Q1 2003 in 100,000 unit quantities.

Samples of the initial six ProASIC Plus devices are currently available.

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