FPGAs hit the performance accelerator
Actel reckons its Axcelerator family comprises the industry's fastest FPGA solutions
Based on a 0.15-micron, seven-layer metal antifuse process, the Axcelerator family, with devices ranging in density from 125,000 to 2-million system gates, will achieve the highest internal performance in the industry, delivering over 500MHz operation and up to 100% resource usage. Until recently, the speed of the internal logic core of most FPGAs has kept up with system performance.
However, with performance requirements for communications systems increasing dramatically, FPGAs are often unable to process data through the chip at wireline speeds, forcing the use of heavy pipelining and redundant logic to achieve the required system throughput.
Developed to address these system requirements and enable maximum system performance, Actel's antifuse-based Axcelerator family virtually eliminates the need for extensive design optimisation techniques required when using traditional SRAM-based FPGAs.
With 2-million system gates, the largest device in this five-member family, the AX2000, contains support for up to 339Kbit of embedded SRAM; 684 user I/Os; 10,752 dedicated flip flops; eight global clocks and eight phase-locked loops (PLLs).
To complement Axcelerator's high densities and high performance, Actel has extended its intellectual property (IP) programme by porting and optimising more than 40 cores with additional support for high-performance interfaces available throughout the year.
The program includes PCI-X, SPI 4.2, HyperTransport, Gigabit Ethernet, HDLC processors, forward error correction cores, a T1/E1 framer, a CRC generator and an 8bit/10bit encoder/decoder.
The first members of the Axcelerator family, the AX1000 and AX2000, offer 1-million and 2-million equivalent system gates, respectively, and are currently available as engineering samples with production scheduled to begin in Q4 2002.
The remaining three devices are expected to be available for sampling by Q4 2002.
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