Product category: Programmable Logic Devices
News Release from: Actel Europe | Subject: AX architecture
Edited by the Electronicstalk Editorial Team on 2 July 2002

Architecture eliminates FPGA bottlenecks

Actel has unveiled its AX architecture, a new FPGA technology specifically developed to the meet the extreme-performance, high-capacity requirements of designers of leading-edge comms systems.

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Actel has unveiled its AX architecture, a new FPGA technology specifically developed to the meet the extreme-performance, high-capacity requirements of designers of leading-edge, next-generation communication systems. AX was crafted with two key objectives in mind - to eliminate the performance bottlenecks and expensive workarounds that exist when using traditional FPGAs pushing the performance envelope; and to provide a scalable, logic-integration platform for future Actel product generations. In optimising the AX solution to address the performance bottleneck, Actel created an architecture that exceeds 500MHz internal core performance, the industry's highest, and will enable devices based on this new platform to eclipse the speed and logic usage of any products currently on the market.

Indeed, with Axcelerator, the first product family based on this AX architecture, Actel reckons it has set a new standard for system-level performance.

To achieve its objectives, Actel integrated a number of new logic, routing, clock management, I/O and embedded features and functionality into the high-performance AX architecture.

"Over the course of its history, Actel has seen FPGA technology evolve to meet the needs of higher and higher speed communications applications.

Actel's new AX architecture represents a new rung on the technology ladder for FPGA architectures", said John East, president and CEO at Actel.

"Users of Actel's FPGAs based on AX now have the performance boost they have been waiting for.

In fact, it is becoming more and more evident that for applications in which speed is critical, Actel is poised to take the leadership position".

The AX architecture features several key advancements.

Included among these are new high-speed, FIFOs for data buffering, an intelligent clock and clock-phase management system, and a scalable, tile-based, high-usage logic structure.

The embedded FIFO control unit contains metastability immune control circuitry that supports high-performance communications design without using general device resources.

The AX architecture is fully fracturable, meaning that if one or more of the logic modules in a SuperCluster are used by a particular signal path, the other logic modules are still available for use by other paths.

As a result, the fully fracturable SuperCluster allows high logic module usage.

The addition of an embedded 64-bit PerPin FIFO enables easy interfacing with off-chip resources on different clock domains.

Available equally across the chip, the AX architecture includes eight PLLs and eight global clocks, which eliminates the need for clock floorplanning and eases design migration.

High-speed applications require a general-purpose FPGA architecture capable of handling high datarates coming on to the chip.

With internal core performance over 500MHz, more than 20% faster than that of the competition, the AX architecture is a suitable platform on which Actel can develop general-purpose and BridgeFPGA solutions for next-generation, high-speed communications applications.

Following the initial five Axcelerator family members, Actel plans to deliver additional derivatives over the next 18 months.

Further capitalising on the high-speed internal core performance of the AX architecture, the first family specifically optimised for bridging applications is expected to sample by the end of 2002.

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