Intellectual Property Cores

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Latest articles from 'Intellectual Property Cores'

News releases from this sub-category

Showing 51-75 of 1567 articles

Evatronix updates its 8051-configurable IP core

Evatronix SA has introduced the R8051XC2, the next generation of its 8051-configurable IP core.

News from Evatronix, Jan 28, 2009

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Tensilica ports RNWK decoders to HiFi 2 Audio DSP

Tensilica has ported the RealAudio 8, 9 and 10 decoders from digital entertainment services company RealNetworks (RNWK) to the HiFi 2 Audio DSP, a licensable audio DSP.

News from Tensilica, Jan 12, 2009

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HiFi 2 DSP simplifies Blu-ray audio processing

Tensilica will demonstrate DTS-HD Master Audio Lossless decoding on the HiFi 2 Audio DSP (digital signal processor), at the Consumer Electronics Show in Las Vegas, 8-11 January 2009.

News from Tensilica, Jan 8, 2009

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LSI launches chipset for IP connections

LSI has unveiled a system-powered, silicon data access arrangement-based foreign exchange office chipset that enables connections between IP applications and conventional analogue lines.

News from LSI Europe, Dec 24, 2008

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LSI announces echo cancellation software

LSI Corporation has announced echo cancellation software for the LSI Starpro range of multicore media processors.

News from LSI Europe, Dec 18, 2008

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Imagination unveils PowerVR silicon core

Imagination Technologies has reported that its PowerVR SGX540 core is now available in silicon.

News from Imagination Technologies, Nov 27, 2008

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Graphics processor achieves OpenGL conformance

Imagination Technologies has reported that its PowerVR SGX520 graphics processor core has achieved conformance with the Khronos OpenGL ES 2.0 standard.

News from Imagination Technologies, Nov 25, 2008

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Imagination adds to VXE video encoder range

Imagination Technologies has announced the availability of two IP cores in the PowerVR VXE video encoder range.

News from Imagination Technologies, Nov 21, 2008

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ARM announces SOI physical IP library

ARM has announced a Silicon-on-Insulator (SOI) physical IP library including standard cell, memory and I/O libraries for IBM's fully enabled 45nm SOI foundry.

News from ARM, Nov 11, 2008

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Evatronix upgrades SDIO-Host controller

Evatronix has released the upgraded SDIO-Host - a full SDIO specification 2.0 compliant host controller available as a single IP core.

News from Evatronix, Nov 5, 2008

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RF Engines adds weight to EE Times survey

RF Engines has added its weight to the latest EE Times survey that reveals the increasing dominance of FPGAs over cell-based ASICs and structured arrays.

News from RF Engines, Oct 23, 2008

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MIPS expands HDMI IP portfolio

MIPS Technologies has announced an expansion of its HDMI IP portfolio, with the industry's first 45nm IP cores (Controller + PHY), as well as 90nm IP cores in silicon.

News from MIPS Technologies, Oct 1, 2008

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Evatronix upgrades NAND IP core

Evatronix has announced an upgrade to its NAND Flash Controller IP core.

News from Evatronix, Sep 3, 2008

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Audio engine adds more Dolby decoders

Additions to the HiFi 2 audio codec library satisfy the needs of designers developing SoCs for home entertainment and multichannel in-car audio systems.

News from Tensilica, Aug 27, 2008

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SystemC specialist supports core activities

CircuitSutra offers comprehensive SystemC services including TLM modelling of complete SoC and individual IP blocks at various abstraction levels.

News from Tensilica, Aug 25, 2008

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Audio IP stars in CE media processor

The new Intel Media Processor integrates the Tensilica's HiFi 2 audio processor.

News from Tensilica, Aug 21, 2008

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Physical layer interface runs up to 6Gbit/s SATA

New multi-interface PHY delivers greater value to drive manufacturers by offering a 35% reduction in die size and 30% reduction in power consumption.

News from STMicroelectronics, Aug 21, 2008

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Alliance aims for COTS IP compliance

Mentor is joining Altera's DO-254 Global Partner Network to set up design and verification best practices for DO 254-certifiable IP development and integration flows.

News from Mentor Graphics UK, Aug 20, 2008

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Graphics cores pass all 2 and 3D tests

World's first 3D graphics acceleration solution to achieve conformance on commercially available production silicon for all of the Khronos mobile 2D and 3D graphics APIs.

News from Imagination Technologies, Aug 19, 2008

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Security library protects IP networks

Enhanced security library provides for encryption, authentication and public key acceleration based in silicon that can secure data at rates exceeding 10Gbit/s.

News from LSI Europe, Aug 18, 2008

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IP sets the gold standard for Intel

Proven interoperability of the DesignWare IP for PCI Express allows designers to lower the risk of integrating PCI-SIG IOV technology into their SoCs.

News from Synopsys, Aug 15, 2008

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IP has all DDR memories covered

The DesignWare DDR IP solutions deliver memory system performance up to 1600Mbit/s - the maximum datarate of the JEDEC DDR3 specification.

News from Synopsys, Aug 14, 2008

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Digital IF design filters spectrum analyser

Advanced SpectraChip IF design acts as a digital replacement for the analogue intermediate frequency filtering section of LIG Nex1's latest instrument.

News from RF Engines, Aug 13, 2008

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3D graphics acceleration proves popular

Patented tiled based deferred rendering architecture is the most optimal and advanced technology for delivering performance and low-power-consumption high-quality 3D graphics.

News from Imagination Technologies, Aug 11, 2008

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Graphics core provides depth of texture

The Depth Texture extension to the OpenGL ES 2.0 application programming interface enables dynamic shadow rendering.

News from Vivante Corporation, Aug 11, 2008

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Showing 51-75 of 1567 articles

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