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?Testbenches?

An Electronicstalk guide

Start with the news release Serial IP core supports RapidIO 2.1 specification from Altera Europe, which we summarised at the time by saying "Altera has announced the first intellectual property (IP) core supporting the RapidIO 2.1 specification. ". Several months prior to that, we featured the news release Designware SATA IP aids 6Gbps data-transfer from Synopsys: "Synopsys's Designware SATA AHCI host and device digital controller IP accelerates the deployment of the 6Gbps interface into solid-state drives and enterprise-class storage-system SoCs. ".

In July 2008, we covered the news from Synopsys - take a look at IP package creates full Serial ATA interface which says: "Comprehensive high quality IP solution helps designers reduce the risk and cost of integrating the Serial ATA interface into their SoC designs.".

Take a look also at the news release from Cadence Design Systems, Verification IP products suit OVM users, as well as Manual formalises low-power verification from Synopsys, and Verification promises gap-free performance from OneSpin Solutions.

Latest stories...
Verification methodology goes online (May 2008)

Synopsys' complete implementation of the VMM methodology is available as a free download.

Verification startup aims to reassure IC designers (May 2008)

Nusym is focused on an "intelligent verification" approach that leverages design insight to automatically drive rapid verification closure.

VMM methodology speeds I/O design (May 2008)

Pairing the VMM methodology with the VCS tool enabled NextIO to efficiently build highly accurate system-level and unit-level simulation environments that quickly identify design bugs.

Systematic verification boosts productivity (February 2008)

Process systematically delivers predictable, repeatable verification results for complex modules and IP, accelerating the gap-free formal verification that ensures first-time error-free operation.

Software rises to formal verification challenges (December 2007)

Ascent finds bugs in RTL designs and improves design quality, with significantly higher performance compared with Real Intent's previous generation of automatic verification software.

Verification line handles complex chip designs (December 2007)

New offerings in the Incisive Enterprise verification family enable users to handle designs containing hundreds of millions of logic gates.

Acquisition addresses power management challenges (June 2007)

ArchPro's silicon-proven power management technologies are a natural fit with Synopsys' advanced verification platform.

Graphical approach eases complex verification (May 2007)

Graph based functional test synthesis tool helps users to understand, define and analyse complicated verification requirements.

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