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"Functional verification"...

Laurence Marchini

Laurence Marchini, Editor, writes:
 

We see from your search that you're looking for information on the term "Functional verification", and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest. Let me be your guide.
 
Start with the news release Language link eases verification from OneSpin Solutions, which we summarised at the time by saying "OneSpin's 360 MV ensures that all functional errors in complex digital modules and intellectual property (IP) are detected". The day before, we featured the news release EDA tools standardise on Unified Power Format from Synopsys: "Standard enables users to create a consistent description of the low power design intent for use by EDA tools for design and verification of today's low power ICs".
 
In November 2007, we covered the news from Cadence Design Systems concerning its Incisive - take a look at Verification plan speeds overall development which says: "Micronas has selected the Cadence Incisive Plan-to-Closure Methodology and Incisive Enterprise Manager for verification planning".
 
Take a look also at the news release from Synopsys, Verification systems handle complex SoCs, as well as Verification kit eases design process from Cadence Design Systems, and Verification library receives approval from Accellera.
 

See also:

Collaboration to improve ASIC verification (May 2007)
Synopsys and Synplicity have agreed to work together on next-generation high-performance verification solutions for ASIC designers

ASIC verification nears full device speed (May 2007)
Software offers full visibility into FPGA-based ASIC and ASSP prototypes enabling designers to find, fix and verify functional errors at speeds approaching that of the final device

Functional verification expands in scope (May 2007)
Platform addresses low-power verification and incorporates verification management capabilities that enable closed-loop management reporting, analysis and documentation

Graphical approach eases complex verification (May 2007)
Graph based functional test synthesis tool helps users to understand, define and analyse complicated verification requirements

Kit cuts the cost of low-power IC design (May 2007)
Design kit enables engineers of different experience levels to adopt advanced low-power techniques with minimal risk and deployment effort

Board sets the stand